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ir3725 data sheet page 1 of 19 www.irf.com 2011_11_16 input power monitor with digital interface features ? accurate power, current, or voltage reporting ? 1.5 % maximum power error ? 1.0 % maximum current error ? serial digital interface ? smbus and i 2 c compatible ? programmable averaging interval ? flexible current sensing ? resistive or inductor dcr ? applications ? synchronous rectified buck converters ? multiphase converters ? 12pin 3x4 dfn lead free ? rohs compliant description the ir3725 is a highly configurable power monitor ic that uses proprietary digital technology to measure a 12v rail current, its voltage, or its average power over a user specified time interval. configuration and result reporting are managed through a serial digital interface. the current is measured as a voltage across a shunt resistance, an input inductor, or a copper trace resistance. the real time voltage and current signals are multiplied, digitized, and averaged over a user selectable averaging interval providin g truepower? measurement of highly dynamic loads. typical application circuit vcs1 l dcr buck regulators vdd i 2 c to system controller ir3725 gnd vcs2 3.3v vt r t c cs1 c cs2 input capacitors 2 +12v 0.1 uf vo addr +12v return alert# ordering information device package order quantity ir3725mtrpbf 12 lead dfn (4x3 mm body) 3000 piece reel ir3725mpbf 12 lead dfn (4x3 mm body) sample quantity
ir3725 data sheet page 2 of 19 www.irf.com 2011_11_16 absolute maximum ratings all voltages referenced to gnd vdd: ................................................................ 3.9v alert#: ........................................................... 3.9v alert# ............................................. < vdd + 0.3v vcs1, vcs2, vo ........................................... 25.0v all other analog and di gital pins ...................... 3.9v operating junction temp erature .... -10c to 150 o c storage temperature range .......... -65 o c to 150 o c thermal impedance ( jc ) .......................... 1.6 c/w thermal impedance ( ja ) ........................... 30 c/w esd rating ......... hbm class 1c jedec standard msl rating .................................................. level 2 reflow temperature ..................................... 260c stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and functional operation of t he device at these or any other conditions beyond those indicated in the operational sections of the specificati ons are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical specifications unless otherwise specified, these specifications apply: vdd = 3.3v 5%, 0 o c t j 125 o c, 8v vo 23.5v, and operation in the typical application circuit. see notes following table. parameter test condition note min typ max unit bias supply vdd turn-on threshold, vdd up 3.1 v vdd turn-off threshold, vdd dn 2.4 v vdd uvlo hysteresis 75 mv vdd operating current r t = 25.5 k ? 700 1000 ? ? voltage reference v t voltage r t = 25.5 k ? 1.40 1.50 1.60 v reference load, r t 1 20 25.5 45.3 k ? voltage sensor voltage, full scale, v fs 23.5 v current sensor voltage, current gain, v ig r t = 25.5 k ? 1.48 v digitizer internal sampling frequency driven from internal clock 512 khz external sampling frequency driven from external clock 922 1024 1126 khz power information minimum averaging interval config reg [d3..d0] = b?0000 1 0.85 1 1.15 ms maximum averaging interval config reg [d3..d0] = b?1000 1 217 256 295 ms
ir3725 data sheet page 3 of 19 www.irf.com 2011_11_16 notes: 1. guaranteed by design, not tested in production 2. assumes no error contribu ted by external components block diagram parameter test condition note min typ max unit accuracy power measurement error vo=12v, dcr voltage = 75 mv, r t =25.5k ? , rcs1=rcs2=1.5k ? 1, 2 2 % t j = 0 - 85 c 1.5 voltage measurement error vo=12 v, dcr voltage = 75mv, rt=25.5k ? , rcs1=rcs2=1.5k ? 1, 2 1.5 % tj = 0 ? 85 c 1.3 current measurement error vo=12v, dcr voltage = 75 mv, r t =25.5k ? , rcs1=rcs2=1.5k ? tj = 0 ? 85 c 1, 2 1.6 %
ir3725 data sheet page 4 of 19 www.irf.com 2011_11_16 pin description name number i/o level description vcs1 1 analog 12v current sensing input 1 vcs2 2 analog 12v current sensing input 2 vo 3 analog 12v voltage sensing input vt 4 analog thermistor sensing input gnd 5 0v ic bias supply and signal ground vdd 6 3.3v 3.3v bias supply extclk 7 3.3v digital input for optional external clock addr 8 3.3v digital bus address selection input scl 9 3.3v digital bus clock; input only sda 10 3.3v digital bus data; input / open drain output alert# 11 3.3v digital programmable output function; open drain output clamped to vdd nc 12 do not connect ic pin functions vdd pin this pin provides operational bias current to circuits internal to the ir3725. bypass it with a high quality ceramic capacitor to the gnd pin. gnd pin this pin returns operational bias current to its source. it is also the reference to which the voltage vo is measured, and it sinks the reference current established by the external resistor r t . vo pin this pin is to be electrically connected to the location in the circuit where voltage for the power calculation is desired to be monitored. power accuracy may be degraded if the voltage at this pin is below vo min . vcs1 and vcs2 pins the average current into these pins is used to calculate power. current sources internal to the ir3725 will null the average voltage between this pin pair. vt function a voltage internal to the ir3725 drives the vt pin while the pin current is monitored and used to set the amplitude of the switched current source it. this pin should be connected to gnd through a precision resistor network rt. this network may include provision for canceling the positive temperature coefficient of the inductor ?s dc resistance (dcr). alert# function the alert# pin is a multi-use pin. during normal use it can be configured via the serial bus as an open drain alert# pin that will be driven logic low when new data is available in the output register. after the output register has been read via the serial bus the alert# will be released to it s high resistan ce state. this pin can also be programmed to pull low when the output exceeds the programmable level.
ir3725 data sheet page 5 of 19 www.irf.com 2011_11_16 addr pin the addr pin is an input that establishes the serial bus address. valid addresses are selected by grounding, floating, or wiring to vdd the addr pin. table 1, ?user selectable addresses?, provides a mapping of possible selections. bypass this pin to gnd with a high quality ceramic capacitor when floated. table 1 user selectable addresses addr pin configuration bus address low b?1110 000 open b?1110 010 high b?1110 110 extclk this pin is a schmitt trigger input for an optional externally provided square wa ve clock. the duty ratio of this externally provided clock, if used, shall be between 40% and 60%. if no external clock is connected, the internal clock will be used. connect this pin to gnd if no external clock is used. scl scl is the serial bus clock and is capable of functioning with a rate as low as 10 khz. it will continue to function as the rate is increased to 400 khz. this device is considered a slave, and therefore uses the scl as an input only. sda sda is monitored as data input during master to slave transactions, and is driven as data output during slave to master transactions as indicated in the packet protocol section to follow.
ir3725 data sheet page 6 of 19 www.irf.com 2011_11_16 typical performance characteristics (one device tested using ?resistor sensing circuit?, vdd = 3.3 v, c cs2 = 10 u f, r t = 25.5 k ? , 90 mv full scale uses r cs1 = r cs2 = 1.5 k ? , 25 mv full scale uses r cs1 = r cs2 = 432 ? , 9 mv full scale uses r cs1 = r cs2 = 150 ? . each data point is average of eight samples.) ir3725 powermode - transfer function (90 mv v dcr full scale) 0 50 100 150 200 250 0.00 0.02 0.04 0.06 0.08 v dc r [v] power codes [of 256] vo = 7 v vo = 12 v vo = 20 v ir3725 powermode - error [% ] (25 mv v dcr full scale) 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 0.000 0.005 0.010 0.015 0.020 0.025 v dcr [v] power error [% of v dcr ] vo = 7 v vo = 12 v vo = 20 v ir3725 powermode - error [% ] (90 mv v dcr full scale) 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 0.00 0.02 0.04 0.06 0.08 v dcr [v] power error [% of v dcr ] vo = 7 v vo = 12 v vo = 20 v ir3725 powermode - error [%] (9 mv v dcr full scale) 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 0.000 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 v dcr [v] p ower error [% of v dcr ] vo = 7 v vo = 12 v vo = 20 v
ir3725 data sheet page 7 of 19 www.irf.com 2011_11_16 ir3725 currentmode - error [% ] (90 mv v dcr full scale) 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 0.00 0.02 0.04 0.06 0.08 v dc r [v] current error [% of v dcr ] vo = 7 v vo = 12 v vo = 20 v ir3725 currentmode - error [% ] (9 mv v dcr full scale) 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 0.000 0.002 0.004 0.006 0.008 v dcr [v] c urrent error [% of v dcr ] vo = 7 v vo = 12 v vo = 20 v ir3725 currentmode - error [%] (25 mv v dcr full scale) 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 0.000 0.005 0.010 0.015 0.020 0.025 v dcr [v] c urrent error [% of v dcr ] vo = 7 v vo = 1 2 v vo = 2 0 v ir3725 currentmode - error [% ] -2% 0% 2% 4% 6% 8% 10% 12% 14% 0.000 0.010 0.020 0.030 0.040 v dcr [v] current error [% of v dcr ] 90 mv fs 25 mv fs 9 mv fs
ir3725 data sheet page 8 of 19 www.irf.com 2011_11_16 functional description please refer to the functional description diagram below. power flow through the inductor is the product of output voltage vo times the inductor current i l . an average voltage v dcr will be developed across the inductor as a result of current flow i l . this voltage will result in a net current flow imbalance into the vcs pins that is equal to v dcr / (rcs1 + rcs2). a voltage nulling circuit inside the ic sinks enough current to equalize the voltages of vcs1 and vcs2. the current required to balance the voltages of these two nodes is reported as a fraction of the current v ig / r t using 256 as the denominator. current will be reported as an integer number of counts in two?s compliment binary format with a range of -256 to 256. positive values will be reported when current flow is in the direction of the current flow arrow in the diagram below. the voltage is reported as a positive integer number of counts equal to (voltage * 256) / v fs . v fs is defined in the electrical specifications. power is reported as an integer number of counts in two?s compliment binary format with a range of -256 to 256. positive values will be reported when current flow is in the direction of the current flow arrow in the diagram below. power expressed in counts will be (power * 256) / (i fs * v fs ) where i fs equals v ig *(rcs1 + rcs2) / (r t *dcr). the full scale power p fs is the product of full-scale voltage and full scale current. r th l dcr vt ir3725 vo vcs1 i l vdd 12v in scl sda vcs2 gnd c cs2 c cs1 addr alert# r p r s r cs1a r cs2a r cs1b r cs2b extclk r t figure 1 functional description diagram
ir3725 data sheet page 9 of 19 www.irf.com 2011_11_16 resistor current sensing application the voltage on the shunt resistor of the circuit below is directly proportional to the current from the source. shunts developing 5 mv to 75 mv at i fs have been used. accuracy is enhanced at the higher voltage. select r t to be a 25.5 k ? 1% or better initial tolerance resistor. sinking current capability of vcs1 or vcs2 is v ig / r t . chose r cs1 and r cs2 such that this current through either of them develops the same voltage that is developed by the shunt at full scale current. c cs2 is the integrator capacitor and should have a ceramic dielectric with a value between 0.1 f and 10 f. vt gnd vcs1 vcs2 r cs2 ir3725 vdd bypass cap vdd shunt r t scl c cs2 vdd 12 v power source vo sda r cs1 alert# addr figure 2 resistor sensing circuit
ir3725 data sheet page 10 of 19 www.irf.com 2011_11_16 inductor dcr current sensing application referring to the functional description diagram, it can be seen that the shunt function can be accomplished by the dc resi stance of the inductor that is already present. omitting the resistive shunt reduces bom cost and increases efficiency. in exchange for these two si gnificant advantages two easily compensated design complications are introduced, a time constant and a temperature coefficient. the inductor voltage sensed between the rcs1 resistors is not simply proportional to the inductor current, but rather is expressed in the laplace equation below. ? ? ? ? ? ? ? ? ? ? dcr l s 1 dcr l l v this inductor time constant is canceled when cs1 cs2 cs1 cs2 cs1 c r r r r 2 dcr l ? ? ? ? ? . let eq cs2 cs1 cs2 cs1 r r r r r ? ? ? . a second equation is used to set the full-scale inductor current. ? ? dcr r r r v i cs2 cs1 t ig fs ? ? ? . let sum cs2 cs1 r r r ? ? ? ? . solve for r eq . we now know req and rsum, but we do not know the individual resistor values r cs1 or r cs2 . the next step is to solve for them simultaneously. by substituting r sum into the r eq equation the following can be written: sum cs2 cs1 eq r r r r ? ? , which can then be rearranged to 0 r r r r r sum eq sum cs1 2 cs1 ? ? ? ? ? . note that this equation is of the form 0 c bx ax 2 ? ? ? where a=1, b=-rsum, and c=req?rsum. the roots of this quadratic equation will be r cs1 and r cs2 . use the higher value resistor as r cs1 in order to minimize ripple current in c cs1 . 2 r r 4 1 1 r r sum eq sum cs1 ? ? ? ? ? 2 r r 4 1 1 r r sum eq sum cs2 ? ? ? ? ?
ir3725 data sheet page 11 of 19 www.irf.com 2011_11_16 thermal compensation fo r inductor dcr current sensing the positive temperature coefficient of the inductor dcr can be compensated if r t varies inversely proportional to the dcr. dcr of a copper coil, as a function of temperature, is approximated by ) ) ( 1 ( ) ( ) ( cu r r tcr t t t dcr t dcr ? ? ? ? ? . (1) t r is some reference temperature, usually 25 c, and tcr cu is the resistive temperature coefficient of copper, usually assumed to be 0.39 %/c near room temperature. note that equation 1 is linearly increasing with temperature and has an offset of dcr(t r ) at the reference temperature. if r t incorporates a negative temperature coefficient thermistor then temperatur e effects of dcr can be minimized. consider a circ uit of two resistors and a thermistor as shown in the r t network below. rs rth rp figure 3 r t network if rth is an ntc thermistor then the resistance of the network will decrease as temperature increases. unfortunately, most thermistors exhibit far more variation with temperature than copper wire. one equation used to model thermistors is ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 1 0 ) ( ) ( t t th th e t r t r ? (2) where r th (t) is the thermistor resistance at some temperature t, r th (t 0 ) is the thermistor resistance at the reference temperature t 0 , and is the material constant provided by the thermistor manufacturer. kelvin degrees are used in the exponential term of equation 2. if r s is large and r p is small, the curvature of the equivalent network resistance can be reduced from the curvature of the thermistor alone. although the exponential equation 2 can never compensate linear equation 1 at all temperatures, a spreadsheet can be constructed to minimize error over the temperature interval of interest. the resistance r t of the network shown as a function of temperature is ? ? ? ? ? ? ? t r 1 r 1 1 r t r th p s t (3) using r th (t) from equation 2. equation 4 may be written as a function of temperature using equations 1 and 3 as follows: ?? ? ? ? ? ? ? ? ? ? t dcr r r t r v t i 2 cs 1 cs t ig fs . (4) with rs and rp as additional free variables, use a spreadsheet to solve equation 4 for the desired full scale current while minimizing the i fs (t) variation over temperature.
ir3725 data sheet page 12 of 19 www.irf.com 2011_11_16 error management component value errors external to the ir3725 contribute to power and cu rrent measurement error. the power reported by the ir3725 is a function not only of actual power or current, but also of products and quotients of r t , r cs1 , r cs2 , dcr (or r shunt ), as well as parameters internal to the ir3725. the tolerance of these components increases the total power or current error. sm all signal resistors are typically available in 1% tolerance, but 0.1% parts are available. shunts are also available at 1% or 0.1% tolerance. the dcr tolerance of inductors can be 5%, but 3% are available. fort unately, it is not typical that worst-case errors woul d systematically stack in one direction. it is statistically likely that a high going value would be paired with a low going value to somewhat cancel the error. because of this, tolerances can be added in quadrature (rss). as an example, a 3% dcr used with a 1% r t , a 1% r cs , and 1.5% ir3725 contributes ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 6 3 015 0 01 0 01 0 03 0 2 2 2 2 error to a typical system. quantization error occurs in digital systems because the full scale is partitioned into a finite number of intervals and the number of the interval containing the measured value is reported. it is not likely that the measured value would correspond exactly to the center of the interval. the error could be as large as half the width of the interval. with a binary word size of eight, full scale is partitioned into 255 intervals. consider a measurement made near full scale. any signal in this interval is less than .2% (one-half of 100% / 256) away from the interval?s center, and would therefore never have more error than that due to quantization. on the other hand, consider a measurement at one-tenth full scale. one-half of an interval size at this level corresponds to 2% of the reported value! relative quantization error increases as the measured value becomes small compared to the full-scale value. quantization error can be reduced by averaging a sequence of returned values. layout guidelines the following guidelines will minimize noise and error. refer to the functional description diagram. 1. bypass vdd to gnd with a high quality ceramic capacitor. 2. place ccs2 close to ic pins vcs1 and vcs2. route vcs1 and vcs2 to the current sensing element as a differential pair. 3. sense the current sensing element at its terminals, kelvin style. current and power will be over reported if printed wire board resistance is included between the sense points. 4. if inductor dcr current sensing is used, place the compensating thermistor near the inductor. route the thermistor leads back to the vicinity of the ic with differential routing. void any vias going to ground along the path back until near the ic. locate the thermistor network (not the thermistor) near the ic. 5. vo should sense the voltage at the point of interest. bypass vo to gnd with a high quality ceramic capacitor near the ic. 6. use an isolated dedicated ground plane connected only to grounded components associated with the ic in the figure. connect this dedicated ground plane at one location to the ground of the monitored voltage. 7. do not connect pin 12 to any electrically active node.
ir3725 data sheet page 13 of 19 www.irf.com 2011_11_16 configuration register a configuration register is maintained via the serial bus mfr_specific_00 command, code # d0h. the low order nibble (d3, d2, d1, d0) contains a binary number n from zero to eight. the averaging interval is 2 n milliseconds. n defaults to zero on start up. the next bit (d4) is to be used as a function shutdown bit. b?1 commands an energy saving shutdown mode, and power on default b?0 commands fully functioning mode. d5 high enables the extclk pin to receive the external clock signal, and default d5 low enables the internal clock. the next two bits (d7, d6) program the output parameter. b?00 causes power to be measured and is the power on default state. b?01 causes voltage to be measured. b?10 causes current to be measured. b?11 is not defined and should not be used. the next bit (d8) is used to configure the alert# pin. b?0 is the power on default, and commands alert# to be pulled low when new data is available. b?1 programs the alert# to pull low when the programmable threshold level is exceeded, whether it is power, voltage, or current. register bits (d15...d9) are the alert# threshold register. if the output register is larger than this register, and if (d8) is b?1, then the alert# pin will pull low. the two least significant bits of the output register are not represented in the alert# threshold register. d15?d9 defaults to zero on start up. the results of a configuration register change will be reflected in the output register after previously requested operations have completed. initialize the configuration register after start up. bit # configuration register d0 averaging interval (lsb) d1 averaging interval d2 averaging interval d3 averaging interval (msb) d4 shutdown d5 external clock d6 output config (lsb) d7 output config (msb) d8 alert# configuration d9 alert# threshold (lsb + 2) d10 alert# threshold d11 alert# threshold d12 alert# threshold d13 alert# threshold d14 alert# threshold d15 alert# threshold (msb)
ir3725 data sheet page 14 of 19 www.irf.com 2011_11_16 output register the output register is loaded with a two?s compliment factor of voltage, current, or power, depending on the last request loaded into the configuration register. serial bus ?direct data format? is used. the value of the output register is to be multiplied by a scale factor that is derived below to yield power, voltage, or current in engineering units of watts, volts, or amps. maximum power is the product of maximum voltage and maximum current. the range of valid output register values is indicated in table 2 below. table 2 output register range of returned values parameter returned value (twos compliment binary) returned value (decimal) fs voltage 0100 0000 0000 0000 256 zero voltage 0000 0000 0000 0000 0 +fs current 0100 0000 0000 0000 256 -fs current 1100 0000 0000 0000 -256 +fs power 0100 0000 0000 0000 256 -fs power 1100 0000 0000 0000 -256 a binary point is implicitly located to the left of the first six least significant figures, as in the example below. syyy yyyy yy.00 0000 the ?s? above is the twos compliment sign bit, and the ?y?s? are the twos compliment integers. six zeros pad out the two byte response. these padding zeros could be considered a factor of the slope, which is allowed by the direct data format. the output register multiplied by its scale factor k x yields the requested quantity in engineering units, volts, amps, or watts. the equations below convert digital counts to engineering units: voltage = counts * v fs / 256 current = counts * v ig * (r cs1 +r cs2 ) / (r t * dcr * 256) power = counts * v fs *v ig *(rcs1 + rcs2) / (r t *dcr*256) there is but one output register, and it holds the measurement type (voltage, current, or power) last requested by the configuration register. it is incumbent upon the user to establish correct configuration before requesting a read. read_vout, read_iout, and read_pout are equivalent in that each returns the contents of the same output register. bit# output register d15:d0 output variable, d0 is lsb reserved command codes command codes d2h through d5h, d7h, and d8h are reserved for manufacturing use only and could lead to undesirable device behavior.
ir3725 data sheet page 15 of 19 www.irf.com 2011_11_16 packet protocol s = start condition w = bus write (0) r = bus read (1) a = acknowledge, = 0 for ack, =1 for nack p = stop condition = master to slave = slave to master bus write configuration register s slave address w a command code a data byte low a data byte high ap s see table 1 0 a 1 1 0 1 0 0 0 0 a d7 d6 d5 d4 d3 d2 d1 d0 a d15 d14 d13 d12 d11 d10 d9 d8 ap bus read configuration register s slave address w a command code a s slave address r a data byte low a data byte high a p s see table 1 0 a 1 1 0 1 0 0 0 0 a s see table 1 1 a d7 d6 d5 d4 d3 d2 d1 d0 a d15 d14 d13 d12 d11 d10 d9 d8 1p bus read_vout (output register for confi guration register data byte low = 01xxxxxx) s slave address w a command code a s slave address r a data byte low a data byte high a p s see table 1 0 a 1 0 0 0 1 0 1 1 a s see table 1 1 a d7 d6 d5 d4 d3 d2 d1 d0 a d15 d14 d13 d12 d11 d10 d9 d8 1p bus read_iout (output register for config uration register data byte low = 10xxxxxx) s slave address w a command code a s slave address r a data byte low a data byte high a p s see table 1 0 a 1 0 0 0 1 1 0 0 a s see table 1 1 a d7 d6 d5 d4 d3 d2 d1 d0 a d15 d14 d13 d12 d11 d10 d9 d8 1p bus read_pout (output register for confi guration register data byte low = 00xxxxxx) s slave address w a command code a s slave address r a data byte low a data byte high a p s see table 1 0 a 1 0 0 1 0 1 1 0 a s see table 1 1 a d7 d6 d5 d4 d3 d2 d1 d0 a d15 d14 d13 d12 d11 d10 d9 d8 1p
ir3725 data sheet page 16 of 19 www.irf.com 2011_11_16 pcb pad and component placement the figure below shows a suggested pad and component placement.
ir3725 data sheet page 17 of 19 www.irf.com 2011_11_16 solder resist the figure below shows a suggested solder resist placement.
ir3725 data sheet page 18 of 19 www.irf.com 2011_11_16 stencil design the figure below shows a suggested solder stencil design.
ir3725 data sheet page 19 of 19 www.irf.com 2011_11_16 package information 4 x 3 mm 12l dfn lead free data and specifications subject to change without notice. this product has been designed and qualified for the consumer market. qualification standards can be found on ir?s web site. ir world headquarters: 233 kansas st., el segundo, californi a 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information .

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